(1) Field of the Invention
This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits.
(2) Description of the Related Art
Matched pairs of transistors are important in precision analog circuits. There are conventional layout methods to design matched pairs in integrated circuit elements, such as cross-coupled metal oxide semiconductor field effect transistor layouts. These methods use a relatively large area of the integrated circuit element and do not handle short channel lengths of about 1.0 micrometer or less effectively.
The layout methods of this invention use a smaller area of the integrated circuit element and produce good matching results at channel lengths as low as 0.8 micrometers.